The present invention relates to reducing static phase offset in timing loops, and in particular, to circuits and methods of reducing static phase offset using commutating phase detectors.
Timing loops are circuits that are used in a wide variety of electronic applications. Timing loops are typically used to generate signals that have particular frequencies, periods, or delays. Such loops include phase locked loops and delay locked loops, for example. FIG. 1A illustrates a phase locked loop architecture, which is one type of timing loop. Phase locked loop (“PLL”) 100A includes a phase detector 110, loop filter 120, voltage controlled oscillator (“VCO”) 130, and may optionally include feedback 140 such as a divider, for example. Phase detector 110 includes two input terminals and an output terminal. The first input terminal receives a reference frequency (“REF”), which may be a digital or analog signal. The second input terminal of phase detector 110 is a feedback signal (“FB”) coupled to the output of VCO 130. Phase detector 110 translates phase differences between the input signals into an output signal. The output of phase detector 110 may be a current into a capacitance in loop filter 120, for example. The output of loop filter 120 is a voltage that controls the frequency of oscillation of VCO 130. The output frequency generated by VCO 130 may be divided by feedback 140 or coupled directly to the feedback input of phase detector 110.
As mentioned above, timing loops are used in a variety of applications. For example, in the design of computer systems, maintaining adequate timing margin between the computer system's clock signal and data is very important. As the frequency of the system clock increases, maintaining adequate timing margin becomes even more difficult. Thus, the design of clock distribution networks for the computer becomes more and more difficult as frequencies increase. One application of a timing loop is a zero delay buffer (“ZDB”), which is shown in FIG. 1B. In ZDB 100B, the output of the VCO is typically fed back directly to the input of the phase detector. In this example, the phase detector is implemented using a phase frequency detector and a charge pump. A ZDB may be used to improve the performance of the clock distribution network in a computer system. A ZDB may be used to regenerate a clock signal to improve drive capability or to regenerate multiple copies of the system clock. An ideal ZDB has an output that is an identical version of the input signal in phase and frequency (e.g., the divider modulus of the feedback shown in FIG. 1A is equal to one). Since the output signal of an ideal ZDB is exactly in phase with the input signal, there would appear to be no delay in the buffer, hence the name “zero delay buffer.” However, in a real application some delay is introduced by non-idealities in the PLL. For example, “static phase offset” is a specification that quantifies the phase difference between the input signal and the output signal. Static phase offset is the average phase offset between the input reference signal received by the PLL and the output of the VCO. In other words, static phase offset is the difference in time between the input and the output signals. Ideally, the static phase offset should be zero seconds for a ZDB. However, in real world applications there is always some phase error between the input and output.
FIG. 1C illustrates another timing loop. Timing loop 100B is a delay locked loop (“DLL”) architecture, which is another type of timing loop. An example delay locked loop includes a phase detector 110, filter 120, and voltage controlled delay 150. An input signal to be delayed is coupled to one input of the voltage controlled delay 150, and a second input of the voltage controlled delay is coupled to the output of phase detector 110. The input signal will be delayed by an amount of time set by a voltage at the output of phase detector 110. The input signal to be delayed is also coupled to one input of phase detector 110, and the output of the voltage controlled delay 150 is coupled to the other input of the phase detector 110. In some applications feedback (such as a divider) may be included between the output of the voltage controlled delay and the input of phase detector 110. Thus, in the absences of static phase offset error, the output of the controlled delay 150 will be precisely in phase with the input signal when the loop is closed.
Typically, the majority of static phase offset error is generated in the phase detector. For example, referring to FIG. 1A, if the delay between REF input of phase detector 110 to the output of the phase detector is the same as the delay from FB input of phase detector 110 to the output then there should be no static phase offset. Similarly, if the circuitry in the phase detector is matched, then there should be no static phase offset. For example, if the phase detector includes a phase frequency detector and charge pump, then if the pull up and pull down currents in the charge pump are matched, then there should be no static phase offset. However, typically the delays are different and the circuitry is mismatched due to manufacturing variations and imperfections.
Static phase offset is problematic in timing loop designs. In particular, static phase offset in timing applications can severely impact the timing margins, such as computer system clock margins described above. Thus, it would be desirable to reduce static phase offset so that the timing margin in computer system clocks can be improved. Such improved timing margins would allow for greater and more robust system performance.
Thus, there is a need for reducing static phase offset in timing loops. The present invention solves these and other problems by providing circuits and methods for reducing static phase offset in timing loops using commutating phase detectors.